View 5962-0153201QYX_8358719.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 features q 25 ns maximum (3.3 volt supply) a ddress access time q dual cavity package c ontains two (2) 512k x 8 industry- standard asynchronous srams; the control architecture allows operation as an 8 -bit data width q ttl compatible inputs and output levels, three-state bidirectional data bus q typical radiation performance - total dose: 50krad(si) - sel immune > 8 0 mev-cm 2 /mg - l et th (0.25) = >10 m ev-cm 2 /mg - s aturated cross section cm 2 per bit, 5. 0e-9 - < 1e- 8 e rrors/bit-day, adams 90% geosynchronous heavy ion q packaging options: - 44- lead bottom brazed dual cfp (bbtfp) (4.6 grams) q standard microcircuit drawing 5962-01532 - qml t and q compliant part introduction the qcots tm ut8q1024k8 q uantified commercial off-the- shelf product is a high-performance 1 m b yte ( 8m bit) c mos static ram built with two individual 524,288 x 8 bit srams with a common output enable. memory access and control is provided by an active low chip enable ( e n), an active low output enable ( g ). this device has a power-down feature that reduces power consumption by more than 90% when deselected . writing to each memory is accomplished by taking one of the chip enable ( e n) input s low and write enable ( w n) inputs low. data on the i/o pins is then written into the location specified on the address pins (a 0 through a 18 ). reading from the device is accomplished by takin g one of the chip enable ( e n) and output enable ( g ) low while forcing write enable ( w n) high. under these conditions, the contents of the memory location specified by the address pins will appear on the i/o pins. only one sram can be read or written at a time. the input/output pins are placed in a high impedance state when the device is deselected ( e n high), the outputs are disabled ( g high), or during a write operation ( e n low and w n low). figure 1. ut8q 1024k8 s ram block diagram 512k x 8 512k x 8 dq(7:0) g a(18:0) e 1 e 0 w 1 w 0 standard products qcots tm ut8q 1024k8 s ram data sheet january, 2003
2 pin names notes: 1. to avoid bus contention, on the dq(7:0) bus, only one e n can be driven low simultaneously while g is low. device operation each die in the ut8 q1024k8 h as three control inputs called enable ( e n), write enable ( w n), and output enable ( g ); 19 address inputs, a(18:0); and eight bidirectional data lines, dq(7:0). the device enable ( e n) controls device selection, active, and standby modes. asserting e n enables the device, causes i dd to rise to its active value, and decodes the 19 address inputs to each memory die . w n controls read and write operations. during a read cycle, g must be asserted to enable the outputs. table 1. device operation truth table notes: 1. ?x? is defined as a ?don?t care? condition. 2. device active; outputs disabled. read cycle a combination of w n greater than v ih (min) with e n and g less than v il (max) defines a read cycle. read access time is measured from the latter of device enable, output enable, or valid address to valid data output. sram r ead cycle 1, the address access is initiated by a change in address inputs while the chip is enabled with g asserted and w n deasserted. valid data appears on data outputs dq(7:0) after the specified t avqv is satisfied. outputs remain active throughout the entire cycle. as long as device enable and output enable are active, the address inputs may change at a rate equal to the minimum read cycle time (t avav ). sram r ead cycle 2, the chip enable-controlled access is initiated by e n going active while g remains asserted, w n remains deasserted, and the addresses remain stable for the entire cycle. after the specified t etqv is satisfied, the eight-bit word addressed by a(18:0) is accessed and appears at the data outputs dq(7:0). sram r ead cycle 3, the output enable-controlled access is initiated by g going active while e n is asserted, w n is deasserted, and the addresses are stable. read access time is t glqv unless t avqv or t etqv have not been satisfied. a(18:0) address dq(7:0) data input/output e n device enable w n writeenable g output enable v dd power v ss ground figure 2. 25ns sram pinout (44) 1 44 2 43 3 42 4 41 5 40 6 39 7 38 8 37 9 36 10 35 11 34 12 33 13 32 14 31 15 30 16 29 17 28 18 27 19 26 20 25 21 24 22 23 nc e2 nc a18 a17 a16 a15 g dq7 dq6 v ss v dd dq5 dq4 a14 a13 a12 a11 a10 nc nc nc nc nc a0 a1 a2 a3 a4 e1 dq0 dq1 v dd v ss dq2 dq3 w1 a5 a6 a7 a8 a9 w2 nc g w n e n i/o mode mode x 1 x 1 3-state standby x 0 0 data in write 1 1 0 3-state read 2 0 1 0 data out read
3 write cycle a combination of w n less than v il (max) and e n less than v il (max) defines a write cycle. the state of g is a ?don?t care? for a write cycle. the outputs are placed in the high-impedance state when either g is greater than v ih (min), or when w n is less than v il (max). write cycle 1, the write enable-controlled access is defined by a write terminated by w n going high, with e n still active. the write pulse width is defined by t wlwh when the write is initiated by w n, and by t etwh when the write is initiated by e n. unless the outputs have been previously placed in the high- impedance state by g , the user must wait t wlqz before applying data to the eight bidirectional pins dq(7:0) to avoid bus contention. write cycle 2, the chip enable-controlled access is defined by a write terminated by the former of e n or w n going inactive. the write pulse width is defined by t wlef when the write is initiated by w n, and by t etef when the write is initiated by the e n going active. for the w n initiated write, unless the outputs have been previously placed in the high-impedance state by g , the user must wait t wlqz before applying data to the eight bidirectional pins dq(7:0) to avoid bus contention. typical radiation hardness the ut8q 1024k8 s ram incorporates features which allow operation in a limited radiation environment. table 2. typical radiation hardness design specifications 1 notes: 1. the sram will not latchup during radiation exposure under recommended operating conditions. 2. 90% worst case particle environment, geosynchronous orbit, 100 mils of aluminum. total dose 50 krad(si) nominal heavy ion error rate 2 < 1e -8 errors/bit-day
4 absolute maximum ratings 1 (referenced to v ss ) notes: 1. stresses outside the listed absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. e xposure to absolute maximum rating conditions for extended periods may affect device reliability and performance. 2. maximum junction temperature may be increased to +175 c during burn-in and steady-static life. 3. test per mil-std-883, method 1012. recommended operating conditions symbol parameter limits v dd dc supply voltage -0. 5 t o 4.6v v i/o voltage on any pin -0. 5 t o 4.6v t stg storage temperature -65 to +150 c p d maximum power dissipation 1.0w (per byte) t j maximum junction temperature 2 +150 c q jc thermal resistance, junction-to-case 3 10 c/w i i dc input current 10 ma symbol parameter limits v dd positive supply voltage 3.0 to 3.6v t c case temperature range -40 to +125 c v in dc input voltage 0v to v dd
5 dc electrical characteristics (pre/post-radiation)* (- 40 c to +125 c) (v dd = 3.3v + 0.3) notes: * post-radiation performance guaranteed at 25 c per mil-std-883 method 101 9. 1. measured only for initial qualification and after process or design changes that could affect input/output capacitance. 2. supplied as a design limit but not guaranteed or tested. 3. not more than one output may be shorted at a time for maximum duration of one second. symbol parameter condition min max unit v ih high-level input voltage (cmos) 2.0 v v il low-level input voltage (cmos) 0.8 v v ol1 low-level output voltage i ol = 8ma, v dd =3.0v 0.4 v v o l2 low-level output voltage i ol = 200 m a,v dd =3.0v 0.08 v v oh 1 high-level output voltage i oh = -4ma,v dd =3.0v 2.4 v v oh 2 high-level output voltage i oh = -200 m a,v dd =3.0v v dd -0.10 v c in 1 input capacitance | = 1mhz @ 0v 2 0 pf c io 1 bidirectional i/o capacitance | = 1mhz @ 0v 24 pf i in input leakage current v ss < v in < v dd, v dd = v dd (max) -2 2 m a i oz three-state output leakage current 0v < v o < v dd v dd = v dd (max) g = v dd (max) -2 2 m a i os 2, 3 short-circuit output current 0v < v o < v dd -90 90 ma i dd (op) supply current operating @ 1mhz inputs: v il = 0.8v, v ih = 2.0v i out = 0ma v dd = v dd (max) 1 50 ma i dd1 (op) supply current operating @40mhz inputs: v il = 0.8v, v ih = 2.0v i out = 0ma v dd = v dd (max) 220 ma i dd 2 ( sb) nominal standby supply current @0mhz inputs: v il = v ss i out = 0ma e n = v dd - 0.5, v dd = v dd (max) v ih = v dd - 0.5v 4 25 ma ma -40 c and 25 c +125 c
6 ac characteristics read cycle ( pre/ post-radiation)* (- 40 c to +125 c) (v dd = 3. 3v + 0.3) notes: * post-radiation performance guaranteed at 25 c per mil-std-883 method 1019. 1. functional test. 2. three-state is defined as a 30 0mv change from steady-state output voltage. 3. the et (enable true) notation refers to the falling edge of e n. seu immunity does not affect the read parameters. 4. the ef (enable false) notation refers to the rising edge of e n. seu immunity does not affect the read parameters. symbol parameter min max unit t avav 1 read cycle time 25 ns t avqv read access time 25 ns t axqx 2 output hold time 3 ns t glqx 2 g -controlled output enable time 0 ns t glqv g -controlled output enable time (read cycle 3) 10 ns t ghqz 2 g -controlled output three-state time 10 ns t etqx 2,3 e n-controlled output enable time 3 ns t etqv 3 e n-controlled access time 2 5 ns t efqz 1,2,4 e n-controlled output three-state time 10 ns { { } } v load + 300mv v load - 300mv v load v h - 300mv v l + 300mv active to high z levels high z to active levels figure 3. 3-volt sram loading
7 assumptions: 1. e n and g < v il (max) and w n > v ih (min) a(18:0) dq(7:0) figure 4a . sram read cycle 1: address access t avav t avqv t axqx previous valid data valid data assumptions: 1. g < v il (max) and w n > v ih (min) a(18:0) figure 4b . sram read cycle 2: chip enable-controlled access e n data valid t efqz t etq x t etq v dq(7:0) figure 4c . sram read cycle 3: output enable-controlled access a(18:0) dq(7:0) g t ghqz assumptions: 1. e n < v il (max) and w n > v ih (min) t glqv t glqx t avqv data valid
8 ac characteristics write cycle ( pre/ post-radiation)* (- 40 c to +125 c) (v dd = 3. 3v + 0.3) notes : * p ost-radiation performance guaranteed at 25 c per mil-std-883 method 101 9. 1 . functional test performed with outputs disabled ( g high). 2. t hree-state is defined as 30 0mv change from steady-state output voltage . symbol parameter min max unit t avav 1 write cycle time 25 ns t etwh device enable to end of write 20 ns t avet address setup time for write ( e n - controlled) 0 ns t avwl address setup time for write ( w n - controlled) 0 ns t wlwh write pulse width 20 ns t whax address hold time for write ( w n - controlled) 2 ns t efax address hold time for device enable ( e n - controlled) 2 ns t wlqz 2 w n - controlled three-state time 10 ns t whqx 2 w n - controlled output enable time 5 ns t etef device enable pulse width ( e n - controlled) 20 ns t dvwh data setup time 15 ns t whdx 2 data hold time 2 ns t wlef device enable controlled write pulse width 20 ns t dvef 2 data setup time 15 ns t efdx data hold time 2 ns t avwh address valid to end of write 20 ns t whwl 1 write disable time 5 ns
9 assumptions: 1. g < v il (max). if g > v ih (min) then qn(8:0) will be in three-state for the entire cycle. 2. g high for t avav cycle. w n t avwl figure 5a . sram write cycle 1: write enable - controlled access a(18:0) q(7:0) e n t avav 2 d(7:0) applied data t dvwh t whdx t etwh t wlwh t whax t whqx t wlqz t avwh t whwl t efdx assumptions & notes: 1. g < v il (max). if g > v ih (min) then q(7:0) will be in three-state for the entire cycle. 2. either e n scenario above can occur. 3 . g high for t avav cycle. a(18:0) figure 5b . sram write cycle 2: chip enable - controlled access w n e n d(7:0) applied data e n q(7:0) t wlqz t etef t wlef t dvef t avav 3 t avet t avet t etef t efax t efax or
10 data retention characteristics (pre/post-irradiation) (1 second data retention test) notes: 1. e n = v dd - .2v, all other inputs = v dr or v ss . 2. data retention current (i ddr ) tc = 25 o c. 3. not guaranteed or tested. data retention characteristics (pre /post-ir radiation) (10 second data retention test, t c =-40 o c to +125 o c) notes: 1 . performed at v dd (min) and v dd (max). 2. e n = v ss , al l other inputs = v dr or v ss . 3. n ot guaranteed or tested. symbol parameter minimum maximum unit v dr v dd for data retention 2.0 -- v i ddr 1 ,2 data retention current (per byte) -- 4 .0 ma t efr 1, 3 chip select to data retention time 0 ns t r 1, 3 operation recovery time t avav ns symbol parameter minimum maximum unit v d d 1 v dd for data retention 3.0 3.6 v t efr 2, 3 chip select to data retention time 0 ns t r 2, 3 operation recovery time t avav ns v dd data retention mode t r 50% 50% v dr > 2. 0v figure 7. low v dd data retention waveform t efr e n
11
12 packaging 1. all exposed metalized areas must be plated per mil-prf-38535. 2. the lid is electrically connected to v ss . 3. index mark configuration is optional. 4. total weight is approx. 4.6 g. figure 9. 44-lead bottom brazed dual cfp (bbtfp) package
13 ordering information 1024k8 sram: notes: 1. lead finish (a,c, or x) must be specified. 2. if an ?x? is specified when ordering, then the part marking will match the lead finish and will be either ?a? (solder) or ?c? (g old). 3. prototype flow per utmc manufacturing flows document. tested at 25 c only. lead finish is gold only. radiation neither tested nor guaranteed. 4. extended industrial temperature range flow per utmc manufacturing flows document. devices are tested at -40 c to +125 c. radiation neither tested nor guaranteed. device type: - = 25 ns access, 3.3v operation package type: (u) = 44-lead bottom brazed dual cfp (bbtfp) screening: (p) = prototype flow (w) = extended industrial temperature range flow ( -40 o c to +125 o c) lead finish: (a) = hot solder dipped (c) = gold (x) = factory option (gold or solder) ut8q1024k8 - * * * * aeroflex utmc core part number
14 1024k8 sram: smd 5962 - 01532 * * * notes: 1. lead finish (a, c, or x) must be specified. 2. if an "x" is specified when ordering, part marking will match the lead finish and will be either "a" (solder) or "c" (gold). 3. total dose radiation must be specified when ordering. federal stock class designator: no options total dose (-) = none (d) = 1e4 (10krad(si) ) (p) = 3e4 (30krad(si)) (contact factory) (l) = 5e4 (50krad(si)) (contact factory) drawing number: 01532 device type 01 = 25ns access time, 3.3v operation, extended industrial temp (-40 o c to +125 o c) class designator: (t) = qml class t (q) = qml class q case outline: (y) = 44- lead dual cavity cfp lead finish: (a) = hot solder dipped (c) = gold (x) = factory option (gold or solder) * *

▲Up To Search▲

Price & Availability of 5962-0153201QYX

	To Download 5962-0153201QYX Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .